Emulators have been developed to assist circuit designers in designing and debugging highly complex integrated circuits. An emulator includes hardware that imitates the operations of a circuit under test (also referred to as a design under test (DUT)). By using an emulator to imitate the operations of a DUT, designers can verify that a DUT complies with various design requirements prior to a fabrication.
IC designs are typically described in a HDL language such as Verilog or VHDL. Software can execute on an embedded processor inside the HDL design and the processor execution state can be logged to a file during the model execution. Existing tools can take this software log or database and provide a post-process debug capability that allows the verification engineer to step forward and/or backwards through the recorded embedded software execution.
Post process debug solutions include the processor-state to be recreated at any point in time. The debugger analyzes the following items: program counter, status registers, processor registers, and memory read/write transactions.
The processor execution log generated through emulation is difficult to analyze. The processor execution log typically contains a time-stamp, program counter, register values and all embedded processor to cache memory read/write transactions. In one aspect, the amount of processor execution log can exceed, for example, over 5 Gigabytes, and processing this large log is not feasible or efficient in a post-process debug tool. In another aspect, the memory state stored in the emulator includes multiple cache levels, SoC-interconnect, and memory-controller, and address/data values for any memory item stored by emulator is heavily design dependent. For these reasons, the processor's view of memory cannot be easily extracted from the emulation system.
Therefore, conventional emulation environment is inefficient in terms of hardware and communication resources employed for debugging operations of an embedded processor of a DUT.